회사 블로그 Supply TI Interface Product:Automatic Test Equipment,Digital & Analog I/O,SerDes & GMSL

Supply TI Interface Product:Automatic Test Equipment,Digital & Analog I/O,SerDes & GMSL

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In the fields of semiconductor automatic test equipment (ATE), signal acquisition, in-vehicle perception testing and high-speed measurement instruments, interface links form the core backbone of the system’s performance. TI offers a comprehensive range of interface products, covering digital and analogue I/O, general-purpose high-speed SerDes, and V3Link/FPD-Link automotive-grade SerDes. These enable the construction of complete link solutions—ranging from DUT pin-level electronic units, high-density analogue acquisition and high-speed inter-board interconnects, to in-vehicle GMSL signal transmission, reception and compliance testing—whilst balancing channel density, synchronisation accuracy, signal integrity and long-term stability for mass production testing.

I. Automatic Test Equipment (ATE) Scenario Requirements and TI’s Interface Positioning

The core requirements of ATE are large-scale parallel testing, low timing skew, high-synchronisation sampling, signal isolation and diagnosability. An ATE comprises pin electronics (PE) cards, parameter measurement units (PMUs), arbitrary waveform generators (AWGs), digitisers and backplane interconnect modules. Traditional parallel wiring presents challenges such as routing explosion, increased crosstalk and limitations on channel expansion; the TI interface solution is specifically designed to bridge three levels: analogue signal acquisition at the DUT end, local digital I/O driving, and high-speed serial transmission between boards and the backplane.

The value of the TI interface in ATE: it transmits multi-channel analogue I/O and parallel digital graphic data via SerDes serial compression, thereby reducing the number of backplane traces; Built-in BIST (self-test), PRBS pattern generation and loopback diagnostics support online link testing, reducing the costs of ATE system-wide debugging and fault localisation; whilst also providing level conversion, isolation, ESD protection and level-driving/receiving devices to adapt to the I/O standards of different DUTs, supporting open-circuit and short-circuit tests, DC parameter measurements, AC timing tests and high-speed interface compliance testing.

II. Digital and Analogue I/O Interfaces: The Foundation of ATE Pin Electronics and Signal Chains

Digital I/O devices handle pattern stimulation, comparison, level driving, reception and load clamping for the DUT, and form the basic building blocks of PE cards. TI provides level converters, high-speed differential transceivers, digital isolators, multiplexers and logic buffers, supporting a variety of voltage standards such as LVCMOS, LVDS and LVPECL. These components allow flexible configuration of drive impedance and edge rates, suppress signal reflections, and adapt to the I/O voltage domains of chips manufactured using different processes. Multi-channel switch arrays support channel switching and multiplexed measurements, enabling time-division switching between voltage-forcing, current-forcing, and voltage/current sampling within the PMU unit.

Analogue I/O interfaces work in close conjunction with high-precision signal chains to provide parameter measurement and synchronous acquisition channels for ATE applications. When paired with high-speed SAR ADCs and precision DACs, alongside multi-channel analogue switches, precision operational amplifiers and voltage references, they enable V/I parameter measurement, leakage current testing and threshold testing of the DUT. A typical reference design, such as TIDA-01051, utilises serialisation devices to aggregate synchronously sampled data from multiple ADCs into an LVDS serial channel, significantly increasing the channel density of a single acquisition board whilst reducing the strain on FPGA pin resources; this is suitable for high-density DAQ and ATE measurement card designs.

Digital I/O emphasises timing, drive capability and channel parallelism; Analogue I/O emphasises offset, temperature drift, bandwidth and synchronous sampling error. TI’s I/O product portfolio is capable of both low-speed DC parameter measurements and supporting medium- to high-speed AC parameters and transient waveform capture, serving as the signal entry point for ATE test channels.

III. General-Purpose SerDes: High-Speed Inter-Board and Backplane Interconnects, and High-Speed Data Channels within ATE Systems

TI’s general-purpose SerDes, Retimer and Redriver series are designed for high-speed, non-video data transmission between ATE backplanes and between boards and the host FPGA. They support interfaces such as LVDS and CML, and feature pre-emphasis, equalisation, programmable output swing, built-in BIST (Bus-In-Self-Test) link self-check, PRBS generation and error detection capabilities.

In ATE systems, data from a large number of PE cards and acquisition cards needs to be aggregated onto the host backplane; the sheer volume of parallel LVDS traces makes routing challenging and ensures synchronisation is difficult to guarantee. SerDes serialises multiple parallel data streams and transmits them via a pair of differential lines, thereby reducing the number of connector pins, minimising crosstalk and extending the transmission distance. SerDes devices such as the TDES960 incorporate built-in link BIST, enabling independent verification of the serial link and reverse control channel integrity without the need for an external stimulus source. They are therefore ideally suited for ATE production line self-tests, equipment factory calibration and on-site fault diagnosis.

Complementary signal redriver and retimer devices are used in scenarios involving long backplanes and multi-card cascading to compensate for transmission losses, restore signal eye diagrams, ensure timing synchronisation between multiple channels, prevent the accumulation of jitter caused by high-speed transmission, and guarantee timing consistency during parallel testing of multiple DUTs. These SerDes are not limited to ATE applications but can also be used for high-speed data feedback in industrial cameras, data acquisition systems and test fixtures.

IV. V3Link SerDes and GMSL Test Solution

GMSL is the mainstream high-speed serial interface for in-vehicle cameras and sensing modules; many ATE and HIL (Hardware-in-the-Loop) systems require support for the mass production testing of GMSL devices and in-vehicle camera modules. TI’s V3Link™ SerDes is a high-speed serial link solution designed for in-vehicle video and raw sensor data transmission, supporting uncompressed video, bidirectional control channels, and Power-over-Coax (PoC), with cables compatible with STP shielded twisted-pair and coaxial FAKRA connectors. It shares a high degree of compatibility with GMSL application scenarios and is widely used in automotive platforms, camera acquisition boards and HIL simulation systems as the transmit/receive link for GMSL test fixtures.

Unlike general-purpose SerDes, V3Link optimises jitter and EMI during long-cable transmission and supports spread-spectrum modulation and remote I²C/UART tunnelling. Whilst transmitting image data, it enables bidirectional transparent transmission of configuration commands and status signals, facilitating the reading and writing of camera module registers and in-circuit configuration by test equipment. In ATE testing scenarios, the V3Link SerDes is frequently integrated into GMSL signal interface boards and image acquisition sub-cards to enable the reception, playback and injection of data streams from GMSL cameras under test, thereby facilitating robustness testing under pixel timing variations, link bit errors and power supply disturbances.

It is important to note the distinction: whilst the GMSL standard itself is led by ADI, TI’s V3Link is a competing automotive-grade SerDes solution; the two often coexist in in-vehicle test benches, with TI’s interface solution handling signal forwarding, isolation, level conversion and backplane interconnects within the test fixture to enable GMSL signals to be routed to the ATE host.